Learn more about ASIC PLD FPGA Digital Logic Design from our Electronic Design Automation directory

About Real Intent - Breakthrough in logic verification. Funded by very experienced people from EDA

Atrenta - The Spyglass suite of tools uses predictive analysis technique that performs structural analysis on Verilog and VHDL RTL to detect design problems in SoCs and ASICs.

CG-CoreEl - Enabling Excellence in VLSI Design

ESNUG - John Cooley's independent newsletter on Synthesis and related silicon design automation software. Originally the e-mail Synopsys Users Group (ESNUG). A compiled set of emails contributed by synthesis tool users and edited by John along with his columns a

Forte Design Systems - Develops software which aids your ASIC flow from design through verification.

Geometry Handling Library - A library for 2-D and 3-D geometric calculation in C

Icarus Verilog Interactive - An Open Source interactive simulator frontend for Verilog and VHDL circuit simulation.

Innoveda - A merging of design software companies

Ivex Design International - Windows-based EDA tools

JAD Research - Provides the VerilogTool software and IP for creating and managing digital designs.

NEF Design - Tools for FPGA design and testing

Tharas Systems - Tharas Systems

TransEDA - Developers of innovative design verification and coverage software.